AMD Training and Rollouts Match Bit for Bit
A vLLM report describes a 200-step Qwen3-8B GRPO run on eight AMD MI300X accelerators with zero log-probability mismatches between Megatron training and vLLM rollouts. The ROCm mechanism extends earlier fully auditable training and TPU evidence. It remains watch-only: this is a developer report, not independently reproduced end-to-end training equivalence. Confirm through released configurations, reproducible runs and adoption by an unrelated RL training team.